The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O modules available in the dsPIC30F device family. The UART is a full-duplex asynchronous system that can communicate with peripheral devices, such as personal computers, RS-232 and RS-485 interfaces.
The primary features of the UART module are:
- • Full-duplex 8- or 9-bit data transmission through the UxTX and UxRX pins
- • Even, Odd or No Parity options (for 8-bit data)
- • One or two Stop bits
- • Fully integrated Baud Rate Generator with 16-bit prescaler
- • Baud rates ranging from 29 bps to 1.875 Mbps at FCY = 30 MHz
- • 4-deep First-In-First-Out (FIFO) transmit data buffer
- • 4-deep FIFO receive data buffer
- • Parity, Framing and Buffer Overrun error detection
- • Support for 9-bit mode with Address Detect (9th bit = 1)
- • Transmit and Receive Interrupts
- • Loopback mode for diagnostic support
The UART module consists of the key important hardware elements:
• Baud Rate Generator
• Asynchronous Transmitter
• Asynchronous Receiver
Figure: UART Simplified Block Diagram
Note: Each dsPIC30F device variant may have one or more UART modules(e.g. dsPIC30F4013 has 2 UART modules). An 'x' used in the names of pins, control/status bits and registers denotes the particular module. Refer to the specific device data sheets for more details.
The UART uses standard non-return-to-zero (NRZ) format (one Start bit, eight or nine data bits, and one or two Stop bits). Parity is supported by the hardware, and may be configured by the user as even, odd or no parity. The most common data format is 8 bits, no parity and one Stop bit (denoted as 8, N, 1), which is the default (POR) setting. The number of data bits and Stop bits, and the parity, are specified in the PDSEL<1:0> (UxMODE<2:1>) and STSEL (UxMODE<0>) bits. An on-chip dedicated 16-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. The UART transmits and receives the LSb first. The UART's transmitter and receiver are functionally independent, but use the same data format and baud rate.
Enabling the UART
The UART module is enabled by setting the UARTEN (UxMODE<15>) bit and UTXEN (UxSTA<10>) bit. Once enabled, the UxTX and UxRX pins are configured as an output and an input, respectively, overriding the TRIS and PORT register bit settings for the corresponding I/O port pins. The UxTX pin is at logic '1' when no transmission is taking place.
The UTXEN bit should not be set until the UARTEN bit has been set. Otherwise, UART transmissions will not be enabled.
bit 15 UARTEN: UART Enable bit
1 = UART is enabled. UART pins are controlled by UART as defined by UEN<1:0> and UTXEN control bits.
0 = UART is disabled. UART pins are controlled by corresponding PORT, LAT, and TRIS bits.
bit 14 Unimplemented: Read as '0'
bit 13 USIDL: Stop in Idle Mode bit
1 = Discontinue operation when device enters Idle mode
0 = Continue operation in Idle mode
bit 12 Unimplemented: Read as '0'
bit 11 Reserved: Write '0' to this location
bit 10 ALTIO: UART Alternate I/O Selection bit
1 = UART communicates using UxATX and UxARX I/O pins
0 = UART communicates using UxTX and UxRX I/O pins
Note: The alternate UART I/O pins are not available on all devices. See device data sheet for details.
bit 9-8 Reserved: Write '0' to these locations
bit 7 WAKE: Enable Wake-up on Start bit Detect During Sleep Mode bit
1 = Wake-up enabled
0 = Wake-up disabled
bit 6 LPBACK: UART Loopback Mode Select bit
1 = Enable Loopback mode
0 = Loopback mode is disabled
bit 5 ABAUD: Auto Baud Enable bit
1 = Input to Capture module from UxRX pin
0 = Input to Capture module from ICx pin
bit 4-3 Unimplemented: Read as '0'
bit 2-1 PDSEL<1:0>: Parity and Data Selection bits
11 = 9-bit data, no parity
10 = 8-bit data, odd parity
01 = 8-bit data, even parity
00 = 8-bit data, no parity
bit 0 STSEL: Stop Selection bit
1 = 2 Stop bits
0 = 1 Stop bit
The heart of the transmitter is the Transmit Shift register (UxTSR). The Shift register obtains its data from the transmit FIFO buffer, UxTXREG. The UxTXREG register is loaded with data in software. The UxTSR register is not loaded until the Stop bit has been transmitted from the previous load. As soon as the Stop bit is transmitted, the UxTSR is loaded with new data from the UxTXREG register (if available).
The UART transmitter block diagram is shown in Figure:
Transmission is enabled by setting the UTXEN enable bit (UxSTA<10>). The actual transmission will not occur until the UxTXREG register has been loaded with data and the Baud Rate Generator (UxBRG) has produced a shift clock (Figure 19-2). The transmission can also be started by first loading the UxTXREG register and then setting the UTXEN enable bit. Normally when transmission is first started, the UxTSR register is empty, so a transfer to the UxTXREG register will result in an immediate transfer to UxTSR. Clearing the UTXEN bit during a transmission will cause the transmission to be aborted and will reset the transmitter. As a result, the UxTX pin will revert to a high-impedance state. In order to select 9-bit transmission, the PDSEL<1:0> bits (UxMODE<2:1>) should be set to '11' and the ninth bit should be written to the UTX9 bit (UxTXREG<8>). A word write should be performed to UxTXREG so that all nine bits are written at the same time.
Transmit Buffer (UxTXB)
Each UART has a 4-deep, 9-bit wide FIFO transmit data buffer. The UxTXREG register provides user access to the next available buffer location. The user may write up to 4 words in the buffer. Once the UxTXREG contents are transferred to the UxTSR register, the current buffer location becomes available for new data to be written and the next buffer location is sourced to the UxTSR register. The UTXBF (UxSTA<9>) status bit is set whenever the buffer is full. If a user attempts to write to a full buffer, the new data will not be accepted into the FIFO. The FIFO is reset during any device Reset, but is not affected when the device enters a Power Saving mode or wakes up from a Power Saving mode.
The transmit interrupt flag (UxTXIF) is located in the corresponding interrupt flag status (IFS) register. The UTXISEL control bit (UxSTA<15>) determines when the UART will generate a transmit interrupt.
1. If UTXISEL = 0, an interrupt is generated when a word is transferred from the transmit buffer to the Transmit Shift register (UxTSR). This implies that the transmit buffer has at least one empty word. Since an interrupt is generated after the transfer of each individual word, this mode is useful if interrupts can be handled frequently (i.e., the ISR is completed before the transmission of the next word).
2. If UTXISEL = 1, an interrupt is generated when a word is transferred from the transmit buffer to the Transmit Shift register (UxTSR) and the transmit buffer is empty. Since an interrupt is generated only after all 4 words have been transmitted, this 'Block Transmit' mode is useful if the user's code cannot handle interrupts quickly enough (i.e., the ISR is completed before the transmission of the next word). The UxTXIF bit will be set when the module is first enabled. The user should clear the UxTXIF bit in the ISR. Switching between the two Interrupt modes during operation is possible. While the UxTXIF flag bit indicates the status of the UxTXREG register, the TRMT bit (UxSTA<8>) shows the status of the UxTSR register. The TRMT status bit is a read only bit, which is set when the UxTSR register is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the UxTSR register is empty.
Setup for UART Transmit
Steps to follow when setting up a transmission:
1. Initialize the UxBRG register for the appropriate baud rate (Section 19.3 "UART Baud Rate Generator (BRG)").
2. Set the number of data bits, number of Stop bits, and parity selection by writing to the PDSEL<1:0> (UxMODE<2:1>) and STSEL (UxMODE<0>) bits.
3. If transmit interrupts are desired, set the UxTXIE control bit in the corresponding Interrupt Enable Control register (IEC). Specify the interrupt priority for the transmit interrupt using the UxTXIP<2:0> control bits in the corresponding Interrupt Priority Control register (IPC). Also, select the Transmit Interrupt mode by writing the UTXISEL (UxSTA<15>) bit.
4. Enable the UART module by setting the UARTEN (UxMODE<15>) bit.
5. Enable the transmission by setting the UTXEN (UxSTA<10>) bit, which will also set the UxTXIF bit. The UxTXIF bit should be cleared in the software routine that services the UART transmit interrupt. The operation of the UxTXIF bit is controlled by the UTXISEL control bit.
6. Load data to the UxTXREG register (starts transmission). If 9-bit transmission has been selected, load a word. If 8-bit transmission is used, load a byte. Data can be loaded into the buffer until the UxTXBF status bit (UxSTA<9>) is set.
Note: The UTXEN bit should not be set until the UARTEN bit has been set. Otherwise,
UART transmissions will not be enabled.
bit 15 UTXISEL: Transmission Interrupt Mode Selection bit
1 = Interrupt when a character is transferred to the Transmit Shift register and as result, the transmit buffer becomes empty
0 = Interrupt when a character is transferred to the Transmit Shift register (this implies that there is at least one character open in the transmit buffer)
bit 14-12 Unimplemented: Read as '0'
bit 11 UTXBRK: Transmit Break bit
1 = UxTX pin is driven low, regardless of transmitter state
0 = UxTX pin operates normally
bit 10 UTXEN: Transmit Enable bit
1 = UART transmitter enabled, UxTX pin controlled by UART (if UARTEN = 1)
0 = UART transmitter disabled, any pending transmission is aborted and buffer is reset. UxTX pin controlled by PORT.
bit 9 UTXBF: Transmit Buffer Full Status bit (Read Only)
1 = Transmit buffer is full
0 = Transmit buffer is not full, at least one more data word can be written
bit 8 TRMT: Transmit Shift Register is Empty bit (Read Only)
1 = Transmit shift register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit shift register is not empty, a transmission is in progress or queued in the transmit buffer
bit 7-6 URXISEL<1:0>: Receive Interrupt Mode Selection bit
11 =Interrupt flag bit is set when Receive Buffer is full (i.e., has 4 data characters)
10 =Interrupt flag bit is set when Receive Buffer is 3/4 full (i.e., has 3 data characters)
0x =Interrupt flag bit is set when a character is received
bit 5 ADDEN: Address Character Detect (bit 8 of received data = 1)
1 = Address Detect mode enabled. If 9-bit mode is not selected, this control bit has no effect.
0 = Address Detect mode disabled
bit 4 RIDLE: Receiver Idle bit (Read Only)
1 = Receiver is Idle
0 = Data is being received
bit 3 PERR: Parity Error Status bit (Read Only)
1 = Parity error has been detected for the current character
0 = Parity error has not been detected
bit 2 FERR: Framing Error Status bit (Read Only)
1 = Framing Error has been detected for the current character
0 = Framing Error has not been detected
bit 1 OERR: Receive Buffer Overrun Error Status bit (Read/Clear Only)
1 = Receive buffer has overflowed
0 = Receive buffer has not overflowed
bit 0 URXDA: Receive Buffer Data Available bit (Read Only)
1 = Receive buffer has data, at least one more character can be read
0 = Receive buffer is empty
bit 15-9 Unimplemented: Read as ‘0’
bit 8 URX8: Data bit 8 of the Received Character (in 9-bit mode)
bit 7-0 URX<7:0>: Data bits 7-0 of the Received Character
bit 15-9 Unimplemented: Read as ‘0’
bit 8 UTX8: Data bit 8 of the Character to be Transmitted (in 9-bit mode)
bit 7-0 UTX<7:0>: Data bits 7-0 of the Character to be Transmitted
UART Baud Rate Generator (BRG)
The UART module includes a dedicated 16-bit baud rate generator. The UxBRG register controls the period of a free running 16-bit timer. Equation shows the formula for computation of the baud rate
The maximum baud rate possible is FCY / 16 (for UxBRG = 0), and the minimum baud rate
possible is FCY / (16 * 65536).
Writing a new value to the UxBRG register causes the BRG timer to be reset (cleared). This
ensures the BRG does not wait for a timer overflow before generating the new baud rate.
bit 15-0 BRG<15:0>: Baud Rate Divisor bits