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SPI - Serial Peripheral Interface

The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link standard which opererate in a full duplex mode. Devices communicate in master or slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select lines with the chip select.




Interface Pins:

The following are the SPI bus logic signals, which in all it has four. These are:
SCLK — Serial Clock (output from master)
MOSI/SIMO — Master Output, Slave Input (output from master)
MISO/SOMI — Master Input, Slave Output (output from slave)
SS — Slave Select (active low; output from master)

Other short convention names are explained below.
SCLK — Serial Clock (output from master)
SDI — Serial Data In
SDO — Serial Data Out
CS — Chip Select (active low; output from master)


SPI Operation:
The SPI bus can operate with a single master device only and with one or more slave devices connected wth tne master device. If a single slave device is used, the SS pin has to be connected logic low. This because the slaves require the falling edge (from high to low state transistion) of the slave select. The following picture describe how a single master and a single slave can be connected togheter, with all the pins needed.



With multiple slave devices, an independent SS signal is required from the master for each slave device. So if there are 4 slave connected to the master, there has to be 4 SS pins on the master so that they can be connected. The following picture shows how a single master and 3 slaves can be connected together with all the pins shown.




1) The first thing to do to begin a communication between the master and the slave is that, the master need to sets the slave select low for the desired chip (either SS1 or SS2 ect..).

2) After this step the master need to wait for some period of timesince the slave have some time delay convertion.

3) The master then generates a clock frequency less than or equal to the maximum frequency the slave device supports. The clock frequecny is usually configured on the master side.

4) During clock generation, a full duplex transmission occurs:
>> the master sends data on the MOSI line; the slave reads from the MOSI line
>> the slave sends data on the MISO line; the master reads from the MISO line


>> Full duplex communication for higher throughput
>> Higher throughput than I²C
>> No addressing means reduced overhead which can be advantageous in small number (if not single) slave.

>> Requires more pins on IC packages:
>> No addressing requires chip selects
>> No hardware flow control
>> No slave acknowledgment (the master could literally be "talking" to nothing and not know it)




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